Title :
Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects
Author :
Higashi, K. ; Yamaguchi, H. ; Omoto, S. ; Sakata, A. ; Katata, T. ; Matsunaga, N. ; Shibata, H.
Author_Institution :
Syst. LSI R&D Center, Toshiba Corp., Tokohama, Japan
Abstract :
In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.
Keywords :
MIS structures; atomic layer deposition; copper; electromigration; integrated circuit interconnections; integrated circuit reliability; tantalum compounds; voids (solid); 140 nm; 45 nm; PVD film; PVD-ALD-PVD stacked barrier metal; TaN; TaN barrier metal; atomic-layer deposition; copper dual-damascene interconnects; electromigration endurance; high performance copper interconnects; highly reliable barrier metal structure; low-k ILD materials; optimal barrier metal structure; stress-induced voiding; wiring resistance; Adhesives; Annealing; Atherosclerosis; Copper; Degradation; Electromigration; Inorganic materials; Testing; Wire; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345664
