A Design Preconditioning Flow for Low-Noise Circuits

Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement, which limits the maximum clock phase insertion between the domains. Therefore, we propose a novel preconditioning flow, which considers noise optimization up front end design, i.e., Design coding stage. By this, RTL-level techniques, such as clock inversion, can be applied to further optimize the noise characteristics, while common current shaping strategies can still be applied in the backend design.