Containment of Metastable Voltages in FPGAs

The significant PVT variations seen with modern technologies make synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature work nicely in principle, but cannot safely handle metastability issues that are inevitable at interfaces even in asynchronous designs. In this paper we propose a reliable implementation of a Schmitt-trigger, which allows to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. Beyond the actual circuit we also discuss the associated routing constraints to make the circuit work properly in spite of the uncertain routing within FPGAs. Furthermore we propose a procedure for an "in situ reliability assessment" of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high-or low-threshold inverters only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.