Design Flow for Radhard TMR Flip-Flops

Protection against radiation effects in digital ASICs chip can be achieved using different design approaches. One of the popular approaches for increasing the reliability is the hardware triplication. However, the hardware triplication does not mean that the susceptibility to radiation effects can be automatically overcome. The automatic random placement of standard cells can result in higher power consumption and more occupied silicon area), with marginal improvement of the linear energy transfer threshold (LET) value. Additionally, the TMR approach usually requires changes in the standard ASIC design flow, even requesting significant modifications of the RTL code. In this paper, we will investigate the issues of design flow for TMR flip-flops, addressing both the issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as the layout generation of radhard TMR flip-flops, based on standard non-hardened flip-flop components.