Device-design metrics to improve manufacturability

Over the past three technology generations we have made systematic observations on device-design strategies leading to optimal circuit-limited yield. These strategies now impose additional considerations that need to be directly coupled into the technology-development paradigm. At the core of the present discussion is the balance between traditional FET (Field Effect Transistor) and small-circuit optimization and the concurrent impact seen at product level. Certain device-design tradeoffs need to be understood in order to maximize performance for a diverse range of products.