Title :
An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0
Author :
Gatta, F. ; Gomez, R. ; Shin, Y. ; Hayashi, T. ; Zou, H. ; Chang, J.Y.C. ; Dauphinee, L. ; Xiao, J. ; Chang, D.S.-H. ; Chih, T.-H. ; Brandolini, M. ; Koh, D. ; Hung, B.J.-J. ; Wu, T. ; Introini, M. ; Cusmai, G. ; Tan, L. ; Currivan, B. ; He, L. ; Cangiane
Author_Institution :
Broadcom, Irvine, CA
Abstract :
This paper reports an embedded dual-tuner architecture able to select two independent 32 MHz frequency bands, allowing for a maximum of 10 demodulated 6 MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0 MHz (CH 0), +6 MHz (CH +1), +12 MHz (CH +2), -6 MHz (CH -1) and -12 MHz (CH -2). Channels +1 and +2 lie at the images of channels -1 and -2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.
Keywords :
CMOS integrated circuits; UHF circuits; circuit tuning; embedded systems; low noise amplifiers; system-on-chip; telecommunication cables; telecommunication channels; DOCSIS 3.0; DS channel demodulation; LNA; RF signal; SoC; data-over-cable system interface specification; digital enhancement; embedded CMOS low-IF dual tuner; frequency 48 MHz to 1 GHz; image rejection; size 65 nm; Bandwidth; Bonding; Error correction; Linearity; Phase detection; Phase locked loops; Power harmonic filters; Radio frequency; Signal to noise ratio; Tuners;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977338
