An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0

This paper reports an embedded dual-tuner architecture able to select two independent 32 MHz frequency bands, allowing for a maximum of 10 demodulated 6 MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0 MHz (CH 0), +6 MHz (CH +1), +12 MHz (CH +2), -6 MHz (CH -1) and -12 MHz (CH -2). Channels +1 and +2 lie at the images of channels -1 and -2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.