Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals

Author

Azais, F. ; David-Grignot, S. ; Latorre, L. ; Lefevre, F.

Author_Institution

LIRMM, Univ. Montpellier, Montpellier, France

fYear

2015

Firstpage

237

Lastpage

242

Abstract

This paper presents an embedded test instrument for on-chip phase noise evaluation of analog/IF signals. The technique relies on 1 -- bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. The module is validated through behavioral and structural simulations. Its implementation in CMOS 140nm technology occupies only 7,885μm2, which represents an extremely small silicon area.

Keywords

CMOS integrated circuits; analogue integrated circuits; built-in self test; digital signatures; phase noise; signal detection; BIST module; CMOS technology; analog-IF signals; digital signature; embedded test instrument; hardware resources; on-chip phase noise evaluation; on-the-fly processing; signal acquisition; size 140 nm; small silicon area; word length 1 bit; Clocks; Frequency measurement; Instruments; Noise measurement; Phase measurement; Phase noise; Semiconductor device measurement; 1-bit acquisition; BIST; Built-In-Self-Test; analog/IF signals; digital signal processing; noise measurement; phase noise; test cost reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on

Conference_Location

Belgrade

Print_ISBN

978-1-4799-6779-7

Type

conf

DOI

10.1109/DDECS.2015.11

Filename

7195703