Title :
On design of fail-safe cellular arrays
Author :
Kamiura, Naotake ; Hata, Yutaka ; Yamato, Kazuharu
Author_Institution :
Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
Abstract :
In this paper, we discuss the design of a fail-safe cellular array composed of switch cells. First, we show the design method using a binary decision diagram. Next, we assume stuck-at-faults of switch cells to be fault models and discuss the fail-safe property for our array. For all the single faults and part of the multiple faults, our array keeps the fail-safe property. Next, for our arrays realizing randomly generated functions, we derive the ratio of the number of double faults that never break the fail-safe property to the total number of double faults. Finally, in order to demonstrate the advantages of our array, we compare our array with other arrays
Keywords :
Boolean functions; cellular arrays; fault diagnosis; logic CAD; logic arrays; logic testing; ternary logic; LSI; binary decision diagram; binary logic function; design method; fail-safe cellular arrays; fault diagnosis; fault models; logic synthesis; multiple faults; number of double faults; randomly generated functions; single faults; stuck-at-faults; switch cells; ternary fail-safe logic; Boolean functions; Circuit faults; Circuit testing; Data structures; Logic arrays; Logic circuits; Multivalued logic; Random number generation; Switches; Switching circuits;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555145
