Title :
CMOS leaf-cell design using simulated annealing
Author :
Wu, Qinghong ; Sloane, Thomas H.
Author_Institution :
Dept. of Electr. Eng., Bucknell Univ., Lewisburg, PA, USA
Abstract :
Describes a program which uses simulated annealing to optimize two-dimensional, full-custom, symbolic CMOS leaf-cell layouts given a circuit-level netlist. User input specifies groups of series and parallel transistor connections with up to three levels of logic hierarchy. Simulated annealing is used for selecting group placements. A new cost function is presented for the simulated annealing algorithm which is based on channel congestion as well as estimated interconnect cost
Keywords :
CMOS integrated circuits; circuit layout CAD; logic CAD; logic arrays; simulated annealing; channel congestion; circuit-level netlist; cost function; group placements; interconnect cost; logic hierarchy; parallel transistor connections; series transistor connections; simulated annealing; symbolic CMOS leaf-cell layouts; CMOS logic circuits; Circuit simulation; Cooling; Cost function; Gaussian distribution; Integrated circuit interconnections; Simulated annealing; Temperature; Topology; Wiring;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271073
