Title :
Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node
Author :
Lee, K.-W. ; Shin, H.J. ; Hwang, J.W. ; Nam, S.W. ; Moon, Y.J. ; Wee, Y.J. ; Kim, I.G. ; Park, W.J. ; Kim, J.H. ; Lee, S.J. ; Park, K.K. ; Kang, H.K. ; Suh, K.-P.
Author_Institution :
Syst. LSI Div., Samsung Electron. Co., Ltd., Kyunggi-Do, South Korea
Abstract :
A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).
Keywords :
copper; dielectric thin films; integrated circuit interconnections; integrated circuit manufacture; silicon compounds; 65 nm; 65nm technology node; Cu; HSQ-via-fill dual damascene process; SiOC; abrasive free low-k direct polishing; advanced ionized PVD; barrier metal; bi-layer dielectric barriers; damage-free capping oxide; highly manufacturable Cu interconnects; low-k dual damascene process; low-k multilevel interconnects; non-porous SiOC film; trench etch stopper; Abrasives; Atherosclerosis; Dielectric devices; Dielectric materials; Etching; Large scale integration; Lithography; Manufacturing processes; Moon; Silicon carbide;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345683
