DocumentCode
1615652
Title
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply
Author
Pu, Yu ; De Gyvez, Jose Pineda ; Corporaal, Henk ; Ha, Yajun
fYear
2009
Firstpage
146
Abstract
Many digital ICs can benefit from sub/near threshold operations that provide ultra-low-energy/operation for long battery lifetime. In addition, sub/near threshold operation largely mitigates the transient current hence lowering the ground bounce noise. This also helps to improve the performance of sensitive analog circuits on the chip, such as delay-lock loops (DLL), which is crucial for the functioning of large digital circuits. However, aggressive voltage scaling causes throughput and reliability degradation. This paper presents SubJPEG, a state of the art multi-standard 65 nm CMOS JPEG encoding coprocessor that enables ultra-wide VDD scaling. With a 0.45 V power supply, it delivers 15 fps 640x480 VGA application with only 1.3 pJ/operation energy consumption per DCT and quantization computation. This co-processor is very suitable for applications such as digital cameras, portable wireless and medical imaging. To the best of our knowledge, this is the largest sub-threshold processor so far.
Keywords
CMOS digital integrated circuits; coprocessors; image coding; CMOS JPEG encoding coprocessor; delay-lock loop; digital IC; digital cameras; energy consumption; frame multistandard JPEG coprocessor; medical imaging; near-threshold power supply; sensitive analog circuit; size 65 nm; ultra-low-energy coprocessor; voltage 0.45 V; Analog circuits; Batteries; Circuit noise; Coprocessors; Degradation; Delay; Digital circuits; Power supplies; Throughput; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-3458-9
Type
conf
DOI
10.1109/ISSCC.2009.4977350
Filename
4977350
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