Title :
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction
Author :
Panigada, Andrea ; Galton, Ian
Author_Institution :
Univ. of California, San Diego, CA, USA
Abstract :
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs.
Keywords :
analogue-digital conversion; calibration; harmonic distortion; DAC noise cancellation; SNDR; calibration technique; digital harmonic distortion correction; integrated digital background calibration techniques; pipelined ADC; power 130 mW; power dissipation reduction; Capacitors; Clocks; Convergence; Delay; Harmonic distortion; Power dissipation; Sampling methods; Solid state circuits; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977358
