CMOS transistor scaling past 32nm and implications on variation

This paper explores CMOS transistor scaling past the 32 nm generation and its implications on variation. Front-end variation sources are reviewed, with detailed discussion on lithography and polish variation sources past 32 nm. New transistor architectures are discussed, with emphasis on benefits and challenges relative to variation. Detailed variation measurement techniques are reviewed, with supporting multi-generational trend results, including data from the 32 nm node.