Design and implementation of high-performance video processor for head-mounted displays

This paper presents the design of a high-performance processor used for head-mounted display (HMD) applications targeting stereo video processing. The proposed hardware architecture of the video processor consists of three major parts: an adaptive 3-dimensional (3D) video decoder to accurately decoding the stereo composite video base band signal (CVBS) source, a video source separation module to generate the 3D display effects while maintaining the original field frequencies on both output channels, and a image post-processing module to enhance the display quality. Furthermore, the paper discusses the key design issue on compact hardware structure for SDRAM access, which is ultimately achieved in a single general SDRAM by data clustering and integration. Both FPGA and ASIC implementations are carried out and the results carefully compared showing that the designed video processor for 3D display could produce well immersing feeling with limited costs in effective decreasing the noise, flicker and crosstalk.