Title :
Formal verification of self-testing properties of combinational circuits
Author :
Kawakubo, Kazuo ; Tanaka, Koji ; Hiraishi, Hiromi
Author_Institution :
Fac. of Eng., Fukuyama Univ., Japan
Abstract :
This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuit´s output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method
Keywords :
Boolean functions; built-in self test; circuit analysis computing; combinational circuits; computability; computational complexity; fault diagnosis; formal verification; logic CAD; logic partitioning; logic testing; Berger code; binary decision diagrams; characteristic functions; combinational circuits; decision function; fault tolerance; formal verification; logic function manipulation; mutiple-input multiple-output circuit; output code words; satisfiability problem; self-checking logic; self-testing properties; stuck-at faults; Binary decision diagrams; Boolean functions; Built-in self-test; Circuit faults; Circuit simulation; Combinational circuits; Computational modeling; Data structures; Formal verification; Logic functions;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555147
