Title :
A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS
Author :
Lidong Chen ; Xuguang Zhang ; Spagna, F.
Author_Institution :
Intel, Santa Clara, CA
Abstract :
This paper presents a power-scalable 5-to-10Gb/s 4-tap DFE that provides further power savings by using three circuit techniques: 1:2 demultiplexed current- integrating summer, sense-amplifier (SA) latched-decision feedback, and fully differential current-recycled DACs (l-DACs).
Keywords :
CMOS integrated circuits; decision feedback equalisers; digital-analogue conversion; low-power electronics; summing circuits; bit rate 5 Gbit/s to 10 Gbit/s; decision-feedback equalization; demultiplexed current-integrating summer; fully differential current-recycled DAC; power 3.6 mW to 5.2 mW; power saving circuit technique; scalable 4-tap DFE; sense-amplifier latched-decision feedback; size 32 nm; Adders; Bit error rate; CMOS technology; Clocks; Decision feedback equalizers; Intersymbol interference; Latches; Output feedback; Solid state circuits; Strontium;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977367
