Identifying design systematics using learning based diagnostic analysis

With billions of transistors being integrated on a single chip by modern VLSI manufacturing processes, traditional yield learning techniques based on defect density present serious drawbacks. Manufacturing process simulation and yield prediction techniques based solely on random defects are increasingly deviating from the actual yields. Design rules are constantly being modified as new design marginalities are uncovered during yield learning, often without much statistical/yield validation. In this paper, we present a new diagnostic technique that merges volume diagnosis data with detailed layout analysis to quantify the true impact of design systematics. The presented technique has been successfully used at IBM to confirm or refute suspected design marginalities on multiple products manufactured in technologies ranging from 90 nm through 45 nm.