A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery

Increasing demand for higher display resolution, greater color data depth, and narrower frame has resulted in increased requirements for higher data rates between the host controller and multiple display driver ICs through fewer transmission channels. To meet these requirements, a clock-embedded interface for LCD displays is presented in this paper. Only one pair of differential 2.0Gb/s serial data is needed to control the LCD driver and to display images. Two key issues for achieving high-speed clock-embedded interfaces in LCD drivers are (1) low-power frequency recovery in each receiver for the operation without a synchronous clock, and (2) stable clock recovery under conditions of high ground noise produced by high-voltage LCD drivers.