Author :
Landers, W. ; Edelstein, D. ; Clevenger, L. ; Das, S. ; Yang, C.-C. ; Aoki, T. ; Beaulieu, F. ; Casey, J. ; Cowley, A. ; Cullinan, M. ; Daubenspeck, T. ; Davis, C. ; Demarest, J. ; Duchesne, E. ; Guerin, L. ; Hawken, D. ; Ivers, T. ; Lane, M. ; Liu, X. ;
Author_Institution :
IBM Semicond. R&D Center, New York, NY, USA
Abstract :
A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K ∼ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM´s internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.
Keywords :
ceramic packaging; chip scale packaging; copper; insulators; integrated circuit interconnections; nanotechnology; plasma CVD; silicon compounds; 90 nm; CVD BEOL insulator; Cu; PECVD low k technology; SiCOH; chip-to-package interaction; dual damascene interconnections; flipchip C4 ceramic package; flipchip C4 organic package; multiple wirebond package; nanometer-technology; stacking; Acceleration; Delamination; Dielectric materials; Dielectrics and electrical insulation; Materials reliability; Semiconductor device packaging; Semiconductor films; Semiconductor materials; Testing; Thermal stresses;
