Voltage contrast test structure for measurement of mask misalignment

A new test structure for measuring mask misalignment for critical levels like contact to gate is described. Alignment requirements have become very challenging because of the extremely small dimensions of current state-of-the-art CMOS devices. The method for measuring contact to gate alignment involves using a SEM to scan an array of contacts each with a different amount of overlap with a grounded gate. The voltage contrast signal indicates which contacts are touching the gate. The data for an example wafer are compared to optical alignment data. Addition work necessary to more thoroughly compare the accuracy of the two techniques is described.