• DocumentCode
    1616336
  • Title

    Infrared microscopy for overlay and defect metrology on 3D-interconnect bonded wafers

  • Author

    Rudack, Andrew C. ; Kong, Lay Wai ; Baker, Greg G.

  • Author_Institution
    SEMATECH, Albany, NY, USA
  • fYear
    2010
  • Firstpage
    347
  • Lastpage
    352
  • Abstract
    Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy provides a way of “seeing” through the silicon where microscopes based on visible wavelengths fail. IR microscopy is used in 3D manufacturing to image sub-surface features (alignment fiducials, defects, and voids) at the interface of bonded wafers. This practical solution enables a variety of through-silicon metrology, including overlay alignment, (e.g., metal 2 to via), review of pre-existing defects from each wafer at the bond interface, and detection of new defects created during the bonding process. IR microscopy is a non-destructive technique and, as such, is an ideal candidate for the in-line metrology required to inspect and monitor the 3D through-silicon via (TSV) interconnect process. This paper reviews the overlay and defect metrology capabilities of IR microscopy. The ability to measure the overlay alignment of bonded wafers according to the 2009 International Technology Roadmap for Semiconductors (ITRS) [1] is demonstrated. Overlay tolerances for a variety of copper interconnect test structures are predicted based on electrical designs, and overlay results are compared to electrical test results. Defect review of bonded wafers is accomplished by “flipping” the defect coordinate system for inverted wafers. The ramifications of adding new defect data to bonded wafer defect files are discussed. The use of IR microscopy to measure wafer pair overlay and to study the interface defectivity of bonded wafer pairs is clearly demonstrated.
  • Keywords
    image processing; integrated circuit interconnections; microscopy; silicon; wafer bonding; 3D interconnect bonded wafers interface; 3D through-silicon via interconnect process; IR microscopy; ITRS; International Technology Roadmap for Semiconductors; TSV interconnect process; copper interconnect test structures; defect coordinate system; defect metrology; electrical designs; image subsurface features; infrared microscopy; microscopes; overlay metrology; through-silicon metrology; visible wavelength; Bonding; Book reviews; Copper; Metrology; Microscopy; Optical microscopy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI
  • Conference_Location
    San Francisco, CA
  • ISSN
    1078-8743
  • Print_ISBN
    978-1-4244-6517-0
  • Type

    conf

  • DOI
    10.1109/ASMC.2010.5551481
  • Filename
    5551481