A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process

Author

Ikegami, Kenshin ; Noguchi, Hiroki ; Kamata, Chikayoshi ; Amano, M. ; Abe, Kiyohiko ; Kushida, K. ; Kitagawa, Eiji ; Ochiai, Toshihiko ; Shimomura, Naoharu ; Kawasumi, A. ; Hara, Hideki ; Ito, Junichi ; Fujita, S.

Author_Institution

Corp. R&D Center, Toshiba Corp., Kawasaki, Japan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

2

Abstract

We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.

Keywords

CMOS memory circuits; MRAM devices; integrated circuit design; magnetic tunnelling; magnetoelectronics; CMOS design; MTJ-last process; SPICE simulation; delay; embedded perpendicular spin transfer torque magnetic random access memory; magnetic tunnel junction; post-layout simulation; structural design space; switching operation; test chip measurement; time 4 ns; upper metal layer; voltage 0.9 V; write voltage embedded perpendicular STT-MRAM; CMOS integrated circuits; Delays; Fabrication; Magnetic tunneling; Metals; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2014.6839663

Filename

6839663