Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs

Author

Sheng-Yen Chien ; Po Yen Lin ; Hung-Yu Chen ; Chrong Jung Lin ; Ya-Chin King

Author_Institution

Inst. of Electron. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

2

Abstract

Self-align nitride (SAN) logic NVM cell coupled by metal gate WL is incorporated into a low-voltage SRAM design. Replacing pull-down transistors in SRAM cells, SAN OTP devices is used to compensate mismatches between the two branches. Through a self-convergent blanket programming operation, the new SRAM cell has been demonstrated to effectively suppress process variation effect, especially critical in low-voltage applications.

Keywords

SRAM chips; embedded systems; integrated circuit design; integrated logic circuits; SAN OTP devices; embedded logic compatible OTP memory; low-voltage SRAM design; low-voltage applications; metal gate WL; one-time programming memory; process variation effect suppression; pull-down transistors; self-align nitride NVM cell; self-convergent blanket programming operation; self-convergent trimming; threshold voltage variation reduction; Monitoring; Nonvolatile memory; Random access memory; Storage area networks; Temperature measurement; Time measurement; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2014.6839666

Filename

6839666