Title :
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS
Author :
Zeng, Raymond ; Chalagalla, Navneet ; Chu, Dan ; Elmhurst, Daniel ; Goldman, Matt ; Haid, Chris ; Huq, Atif ; Ichikawa, Takaaki ; Jorgensen, Joel ; Jungroth, Owen ; Kajla, Nishant ; Kajley, Ravinder ; Kawai, Koichi ; Kishimoto, Jiro ; Madraswala, Ali ; Ma
Author_Institution :
Intel, Folsom, CA
Abstract :
As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device that employs chip architecture, datapath, and analog architecture solutions that address these challenges while meeting high performance requirements. This 32 Gb MLC NAND delivers 50 mus tREAD, 900 mus tPR0G and 9 MB/s write throughput in a 34 nm technology.
Keywords :
CMOS logic circuits; CMOS memory circuits; NAND circuits; flash memories; multivalued logic circuits; CMOS technology; MLC NAND flash memory; analog architecture solutions; bit rate 9 Mbit/s; chip architecture; size 34 nm; time 50 mus; time 900 mus; CMOS technology; Clocks; Decoding; Flash memory; Pipelines; Regulators; Routing; Silicon; Throughput; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977395
