From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

This paper presents a seamless flow of transformations, which performs dedicated, distributed executive generation from a high level specification of a pair: algorithm, architecture. This work is based upon graph models and graph transformations and is part of the AAA methodology. We present an original architecture model, which allows to perform accurate sequencer modeling, memory allocation, and heterogeneous inter-processor communications for both modes shared memory and message passing. Then we present the flow of transformations that leads to the automatic generation of dedicated real-time distributed executives, which are deadlock free. This transformation flow has been implemented in a system level CAD software tool called SynDEx.