Title :
A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS
Author :
Trinh, Cong ; Shibata, Naotaka ; Nakano, T. ; Ogawa, Michiko ; Sato, Jun ; Takeyama, Y. ; Isobe, Keisuke ; Le, Brian ; Moogat, F. ; Mokhlesi, N. ; Kozakai, K. ; Hong, Peilin ; Kamei, Toshihiro ; Iwasa, Koyo ; Nakai, J. ; Shimizu, Tsuyoshi ; Honma, Michino
Author_Institution :
SanDisk, Milpitas, CA, USA
Abstract :
Today NAND flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2 b/cell MLC technology was introduced. Recently MLC NAND flash memories with more than 2 b/cell have been reported. To meet market demands we develop a 5.6 Mb/s 64 Gb 4 b/cell NAND flash memory in 43 nm CMOS. At 5.6 Mb/s, it is suitable for many mainstream applications. The chip has two 32 Gb memory arrays. One NAND string is composed of 66 NAND cells (64 + 2 dummies). With 64 wordlines (WL) per block, 4 pages per WL (4 b/cell), and an 8 KB page size, with block size of 2 MB. The performance is improved with page size extended to 8 KB, by programming 8 KB x 4 b/cell x 2 planes at the same time.
Keywords :
CMOS memory circuits; NAND circuits; flash memories; 4 b/cell memory; CMOS process; NAND flash memory; bit rate 5.6 Mbit/s; high density nonvolatile memory; size 43 nm; storage capacity 64 Gbit; CMOS technology; Circuit testing; Flash memory; Joining processes; Noise level; Noise reduction; Threshold voltage; Throughput; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977400
