Two´s complement systolic multipliers-design and evaluation

Presents and evaluates four systolic architectures for a two´s complement multiplier. Proposes bit-serial architectures for two´s complement multiplication. The multiplication of two binary numbers represented in a two´s complement form is performed using an extended sign-bit technique to avoid correcting the final result. The designs are distinguishable by the method in which the two numbers are introduced to the systolic network. The structures presented are mostly regular, fast, and very area efficient two´s complement systolic multipliers. By maintaining the inherent regularity of a systolic multiplier array, the design time is greatly reduced as only a few basic cells need to be designed. Interconnection wires can be kept short thus reducing the risk of an incorrect circuit. When compared to other systolic array structures, the designs presented are much more area efficient with reduced cell complexity and increased throughput