A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers

Author

Jan, C.-H. ; Anand, Nitin ; Allen, C. ; Bielefeld, J. ; Buehler, M. ; Chikamane, V. ; Fischer, K. ; Jain, A. ; Jeong, J. ; Klopcic, S. ; Marieb, T. ; Miner, B. ; Nguyen, P. ; Schmitz, A. ; Nashner, M. ; Scherban, T. ; Schroeder, B. ; Ward, C. ; Wu, R. ; Z

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2004

Firstpage

205

Lastpage

207

Abstract

A leading edge 90 nm, 300 mm wafer size interconnect technology featuring Cu, CDO low-k ILD and industry´s most aggressive 220 nm minimum metal pitch is being ramped into production for high performance Pentium® microprocessors, the first in industry, to our knowledge. Key enabling features for yield and reliability improvement to resolve challenges from weak thermo-mechanical properties of low k ILD and tight metal pitches for a production worthy interconnect process are presented.

Keywords

copper; integrated circuit interconnections; integrated circuit metallisation; microprocessor chips; 220 nm; 300 mm; 90 nm; CDO low-k ILD interconnects; Cu; Cu metallization; Pentium® microprocessors; interconnect technology; manufacturing logic technology; metal pitch; thermo-mechanical properties; wafers; Capacitance; Degradation; Delamination; Etching; Logic; Manufacturing; Metallization; Microprocessors; Polymer films; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International

Print_ISBN

0-7803-8308-7

Type

conf

DOI

10.1109/IITC.2004.1345747

Filename

1345747