Title :
"Sea of Kelvin" multiple-pattern arrangement interconnect characterization for low-k/Cu dual damascene and its findings
Author :
Okazaki, M. ; Hatano, M. ; Yoshida, K. ; Shibasaki, S. ; Kaneko, H. ; Yoda, T. ; Hayasaka, N.
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Kanagawa, Japan
Abstract :
A very unique multiple pattern arrangement for low-k/Cu interconnect characterization method is introduced. Several hundreds of different shape 4-point probe Kelvin/via/interconnect test patterns are created. With these "Sea of Kelvin" multiple-pattern test structures, 65nm node generation feature size (0.10μm φ via). Low-k/Cu dual damascene interconnect is evaluated. Various aspects of pattern design dependent interconnect characteristics including the influence from the surrounding neighbour patterns are examined. This paper reports this new characterization method and its findings.
Keywords :
copper; dielectric thin films; integrated circuit interconnections; 4-point probe Kelvin; 65 nm; Cu; Cu interconnect; Sea of Kelvin; interconnect test patterns; low-k dual damascene; low-k interconnect; multiple-pattern arrangement interconnect characterization; multiple-pattern test structures; node generation feature size; pattern design; Data engineering; Design engineering; Kelvin; Manufacturing processes; Microelectronics; Probes; Product design; Semiconductor device manufacture; Shape; Testing;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345749
