A 4×4 pipelined intra frame decoder for H.264

Now a number of architectures of intra frame decoder for H. 264 have been put forword, but most of them use an original decoding order. That is current block´s prediction shouldn´t be executed until previous block´s reconstruction is finished. Obviously, this introduces much redundant time. In this paper, we proposed a 4 times 4 pipelined architecture in which current block´s prediction can be paralleled with its previous block´s reconstruction. For intra 4 times 4, we first reorder the original decoding order and then prejudge the pred mode, then the neighboring block´s prediction can be pipelined. For intra 16 times 16 and chroma, we divide them into 4 times 4 blocks, meanwhile, the intra 16 times 16 uses the same decoding order as intra 4 times 4. Furthermore, to enhance the decoding speed, it processes four pixels in parallel in some modules such as inverse quantization, intra prediction and reconstruction. The architecture is implemented in Verilog HDL as a part of H.264 main profile decoder and emulated in FPGA prototyped. Experimental results showed that about 223 to 253 cycles are needed and compared with traditional architecture used by Ting-An Lin et al. (2005) and Ke Xu and Chiu-Sing Choy (2008), about 18 to 23 block´s reconstruction time can be reduced at the expense of only 7 4 bit-comparators to prejudge the pred mode. When running at 62 MHz on Altera Stratix II FPGA, it supports real time decoding with 1080HD video sequence in 30 fps.