Design and implementation of HDLC procedures based on FPGA

High-level data link control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate frame check sequence (FCS) of HDLC-cycle redundancy check (CRC) in FPGA. We verified the methods above by downloading the HDLC modules designed in VHDL (VHSIC hardware description language) into FPGA, which shows the feasibility of the methods. The programming of modules is simple, easy to modify, and superior in practical application.