DocumentCode :
1617400
Title :
Computation of delay defect and delay fault probabilities using a statistical timing simulator
Author :
Benkoski, Jacques ; Strojwas, Andrzej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
1989
Firstpage :
153
Lastpage :
160
Abstract :
Using a formal modeling of the signal interactions, a statistical timing simulator capable of detecting delay faults and computing delay defect distributions has been built. This tool produces the delay fault statistics which must be used by delay fault ATPG (automatic test pattern generation) tools if they are to model process-induced delay failures realistically. The most obvious application for this tool is the computation of the probability of failure due to parametric delay faults. For this application, a Monte Carlo experiment was performed with a single nominal simulation followed by many timing reevaluations
Keywords :
Monte Carlo methods; VLSI; digital simulation; electronic engineering computing; fault location; integrated logic circuits; logic testing; probability; statistical analysis; ATPG; Monte Carlo experiment; VLSI; automatic test pattern generation; delay defect; delay defect distributions; delay fault probabilities; delay fault statistics; logic testing; modeling; parametric delay faults; signal interactions; statistical timing simulator; Automatic test pattern generation; Computational modeling; Delay; Distributed computing; Fault detection; Parametric statistics; Probability; Statistical analysis; Statistical distributions; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
Type :
conf
DOI :
10.1109/TEST.1989.82289
Filename :
82289
Link To Document :
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