Design and performance evaluation of virtual-channel based NoC

New tendencies envisage multiprocessor systems-onchips (MPSoCs) as a promising solution for the high performance Embedding System. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its extensibility and power efficiency. The router is the fundamental unit of NoC. In this paper, a NoC prototype which consists of 6 ARM compatible cores and a router-based on-chip network is designed, and implements on a FPGA device. Different from the prototypes which we formerly designed, this prototype comprises more cores, and virtual-channel routers instead of basic routers. Specially, to evaluate the network performance, we present a run-time network monitor system, which can monitor the performance of on-chip network by calculating the performance parameters, such as average latency and throughput. The experimental results show that this prototype with 2 times 3 virtual-channel routers has less average latency than the former basic router prototype, and improves the throughput by up to 62%. Furthermore, JPEG decoding application is applied on this prototype, which steadily works at 50 MHZ. And the decoding speed of system is very fast because of 2 decoding lane.