Title :
On hardware implementation of fuzzy processing
Author :
Szecówka, Przemyslaw M. ; Musial, Adam
Author_Institution :
Fac. of Microsyst. Electron. & Photonics, Wroclaw Univ. of Technol., Wroclaw, Poland
Abstract :
Digital architecture of fuzzy processor is proposed. All blocks - fuzzy sets (triangular), rule strength calculation (minimum) and defuzzyfication (weighted sum) were implemented in VHDL, verified and synthesized for FPGA. Implementation of floating point division block appeared to be the most difficult part of the design. Partially concurrent and pipelined data flow provides competitive performance, with relatively little dependence on particular algorithm complexity.
Keywords :
computational complexity; field programmable gate arrays; fuzzy set theory; hardware description languages; pipeline processing; FPGA; VHDL; algorithm complexity; defuzzyfication; digital architecture; fuzzy processing; fuzzy sets; hardware implementation; pipelined data flow; rule strength calculation; Clocks; Computer architecture; Field programmable gate arrays; Fuzzy sets; Hardware; Registers; Synchronization; FPGA; VHDL; floating point; fuzzy; hardware;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference
Conference_Location :
Warsaw
Print_ISBN :
978-1-4244-7011-2
Electronic_ISBN :
978-83-928756-4-2
