On the controllability and observability of a class of multiprocessor systems with interleaved memory

A solution for controlling the deadlock situation in a multiprocessor system with multiple buses is examined using the state space approach. Identical processors, totally synchronized with the system clock and communicating through common memory modules, are assumed. A simple Markov chain models the behavior of each processor. The authors have developed state and output equations for the discrete state space model and computed the transition probabilities. Concepts of controllability and observability have been used to avoid the deadlock situation of the processors