Title :
Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels
Author_Institution :
Teradyne Inc., Boston, MA, USA
Abstract :
The test of embedded clusters of conventional logic via boundary scan virtual channels has been shown to be a practical way to test and diagnose structural faults where these clusters are inaccessible to standard ATE (automatic test equipment) channels. Huge quantities of data can be created by this technique, which could result in prohibitive storage requirements and poor throughput. By use of topological data compression and special hardware, the storage requirement can be small and test times limited only by the speed of the boundary scan path. After discussing test pattern generation, the boundary scan environment, and the serialization of test patterns and algorithmic patterns, the author presents applications examples
Keywords :
VLSI; automatic test equipment; integrated logic circuits; integrated memory circuits; logic testing; printed circuit testing; virtual machines; VLSI; VLSI boards; algorithmic patterns; boundary scan path; boundary scan virtual channels; embedded clusters; logic testing; memory clusters; structural faults; test pattern generation; topological data compression; virtual ATE channels; Circuit faults; Circuit testing; Connectors; Fault diagnosis; Fixtures; Integrated circuit interconnections; Logic arrays; Logic circuits; Logic devices; Logic testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82291
