Effects of type and density of interface trap in tunneling oxide for flash memory devices

As the device size in the chip shrinks, shrinking the size of the insulators including tunneling oxide and the inter-poly dielectric is mainly focused on the memory devices. However, the degradation of reliability of insulators is also induced as decreasing the size of chip. In case of flash memory, especially, operation principle is cycling of electrons between floating gate and substrate. So, the degradation is easily caused by the traps caused by tunneling at interface and generation of leakage path through tunneling oxide as scaling down. In this paper, the effects of the trap density and the type of trap at the interface in tunneling oxide are analyzed by using the change of the simulated current density through the tunneling oxide using TCAD model.