Title :
Performance analysis of a hierarchical interconnection network using hypercubes
Author :
Tiruveedhula, V. ; Bedi, J.S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA
Abstract :
Presents an analysis of a mixed class of networks which can be used for interconnection of a large number of processors in which data sharing is very high. This architecture uses both binary hypercubes and a multistage interconnection network with global memory. The shared data are initially kept in the memory modules and a single copy of the data is moved in the network depending on the reference pattern of the system. In this type of architecture, the switches of the network have cache memories and also the capability to maintain directions for indicating the location of the data. However, keeping a single copy in a large system has the advantage of having reduced network traffic and also no overhead due to coherency related activities. The network is evaluated using queuing analysis to take care of the contention in the network. The performance measures are compared with that of a non-hierarchical hypercube system
Keywords :
buffer storage; hypercube networks; multiprocessor interconnection networks; performance evaluation; binary hypercubes; cache memories; data sharing; global memory; hierarchical interconnection network; hypercubes; multistage interconnection network; network traffic; performance analysis; queuing analysis; reference pattern; Cache memory; Computer architecture; Computer networks; Data engineering; Hypercubes; Multiprocessor interconnection networks; Performance analysis; Queueing analysis; Switches; Tree data structures;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271187
