Title :
Spontaneous recovery of positive gate bias stressed power VDMOSFETs
Author :
Stojadinovic, N. ; Manic, I. ; Djoric-Veljkovic, S. ; Davidovic, V. ; Dankovic, D. ; Golubovic, S. ; Dimitrijev, S.
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
fDate :
6/24/1905 12:00:00 AM
Abstract :
Spontaneous recovery of threshold voltage and channel carrier mobility in positive gate bias stressed power VDMOSFETs and the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed. Electron tunneling from neutral oxide traps associated with trivalent silicon ≡Sio. defects into the oxide conduction band is proposed as the main mechanism responsible for stress-induced buildup of positive oxide-trapped charge. Subsequent hole tunneling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis-H is proposed as the dominant mechanism responsible for the interface trap buildup. A chain of mechanisms related to a presence of hydrogen species is proposed in order to explain changes of oxide-trapped charge and interface trap densities during the spontaneous recovery. Interface trap ≡Sis . passivation due to their reaction with hydrogen atoms is proposed as a main mechanism responsible for a decrease of interface trap density. Hydrogen molecule cracking at charged oxide traps ≡Sio+, which leads to their neutralization, is proposed as the dominant mechanism responsible for a decrease of oxide-trapped charge density
Keywords :
carrier mobility; electron traps; hole traps; interface states; passivation; power MOSFET; semiconductor device reliability; tunnelling; Si; channel carrier mobility; electron tunneling; gate oxide-trapped charge; hole tunneling; interface trap densities; interface-trap precursors; molecule cracking; neutral oxide traps; oxide conduction band; positive gate bias stress; power VDMOSFETs; spontaneous recovery; stress-induced buildup; threshold voltage; Artificial satellites; Electron traps; Hydrogen; Ionizing radiation; Passivation; Power supplies; Silicon; Stress; Threshold voltage; Tunneling;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003358