An efficient compact test generator for IDDQ testing

We present an algorithm for generating compact test sets for I_DDQ testing. The faults considered are: (1) the bridging faults (BFs) between gates and (2) the leakage faults (LFs) within a gate. For the LFs within a gate, we propose a fault model called the Input Fault model (IF). The advantages of the IF model include: (1) it is independent of the physical implementation of the logic design, (2) it guarantees the detection of all internal LFs for any implementation, and (3) the total number of faults is relatively small. We utilize the detectability to guide target fault selection during test generation which leads to a compact set of final patterns. We extend the essential fault (ESF) concept and use it for evaluating the detectability of each fault implicitly. The experimental results show that the size of test set generated based on the proposed method is smaller than those obtained by previously proposed procedures