Title :
An efficient compact test generator for IDDQ testing
Author :
Kondo, Hisashi ; Cheng, Kwang-Ting
Author_Institution :
LSI Div., Kawasaki Steel Corp., Chiba, Japan
Abstract :
We present an algorithm for generating compact test sets for IDDQ testing. The faults considered are: (1) the bridging faults (BFs) between gates and (2) the leakage faults (LFs) within a gate. For the LFs within a gate, we propose a fault model called the Input Fault model (IF). The advantages of the IF model include: (1) it is independent of the physical implementation of the logic design, (2) it guarantees the detection of all internal LFs for any implementation, and (3) the total number of faults is relatively small. We utilize the detectability to guide target fault selection during test generation which leads to a compact set of final patterns. We extend the essential fault (ESF) concept and use it for evaluating the detectability of each fault implicitly. The experimental results show that the size of test set generated based on the proposed method is smaller than those obtained by previously proposed procedures
Keywords :
CMOS logic circuits; automatic testing; design for testability; fault diagnosis; integrated circuit testing; logic testing; ATPG; CMOS IC; IDDQ testing; IC testing; algorithm; bridging faults; compact pattern generation; detectability; deterministic pattern generation; efficient compact test generator; essential fault concept; essential faults extraction; fault collapsing; input fault model; leakage faults; logic testing; quiescent current testing; random pattern generation; screening pattern selection; target fault selection; test set size; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit modeling; Integrated circuit testing; Phasor measurement units; Steel; Test pattern generators; Voltage;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555156
