Title :
A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing
Author :
Shen, S.A. ; Shuang Xie ; Wai Tung Ng
Author_Institution :
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper presents a 4-bit windowed delay line ADC implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC is measured to consume a power of 14 μW with ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delay lines; resistors; -chip voltage sensing; CMOS delay line ADC; ENOB; VLSI dynamic voltage scaling power management applications; frequency 4 MHz; power 14 muW; resistors; size 65 nm; voltage 0.87 V to 1.32 V; word length 4 bit; CMOS integrated circuits; Clocks; Delay lines; Delays; Linearity; Resistors; Voltage measurement; analog to digital converter; delay line; low power; power management;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482807
