Title :
Simulation of Si-Ge BiCMOS ESD structures operation including spatial current instability mode
Author :
Vashchenko, V. ; Hopper, P.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
A 2D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, has been presented. The method is used to provide physical evaluation of a safe operation regime of ESD protection structures and circuits. First results of ESD stress induced hot spot formation using 3D simulation have been presented for the case of a simplified snapback n-MOS device
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; circuit simulation; electrostatic discharge; protection; semiconductor materials; temperature distribution; 2D simulation approach; 3D simulation; ESD protection structures; ESD stress induced hot spot formation; SiGe; SiGe BiCMOS ESD structure operation simulation; current stratification; electro-thermal instability; safe operation regime; simplified snapback n-MOS device; spatial current instability mode; BiCMOS integrated circuits; Circuit simulation; Clamps; Degradation; Electrostatic discharge; Equivalent circuits; Protection; Pulse circuits; Stress; Temperature;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003364
