Title :
Board-level boundary-scan: regaining observability with an additional IC
Author :
Ballew, W.D. ; Streb, L.M.
Author_Institution :
AT&T-NS, Oklahoma City, OK, USA
Abstract :
The Probe, a CMOS ASIC (application-specific integrated circuit) that can be used to regain observability lost to higher gate-to-pin ratios and packaging density is described both functionally and technically. This hardware solution will allow board-level designs to look like total boundary scan. The economic feasibility depends on how rapidly present designs move forward: successful application depends heavily on the adoption of P1149.1. The Probe solution offers an opportunity to fuse old and new silicon technologies into a single hierarchical test strategy
Keywords :
CMOS integrated circuits; application specific integrated circuits; automatic test equipment; computer interfaces; printed circuit testing; standards; CMOS ASIC; IC technology; P1149.1; PCB; Probe; SMT; Si; VLSI; application-specific integrated circuit; board-level designs; boundary-scan; economic feasibility; gate-to-pin ratios; hierarchical test strategy; observability; packaging density; standards; Application specific integrated circuits; Circuit testing; Environmental economics; Integrated circuit technology; Manufacturing; Observability; Pins; Probes; Silicon; Surface-mount technology;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82293
