A Digital Phase-locked Loop based on MAP in PLC

Author

Wu, Zhilan

Author_Institution

Inst. of Intell. Inf. Process., Guizhou Normal Univ., Guiyang, China

fYear

2009

Firstpage

76

Lastpage

79

Abstract

The conventional DPLLs (digital phase-locked loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced Class A noise model in PLC first, and then proposed an optimum DPLL for such Class A noise environment using the techniques based on MAP (maximum A posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under Class A noise environment.

Keywords

Gaussian distribution; carrier transmission on power lines; digital phase locked loops; impulse noise; noise (working environment); Gaussian noise environment; MAP techniques; digital phase-locked loop; impulsive noise; power line communication; power line noise; statistical feature; Bandwidth; Clocks; Gaussian noise; Phase locked loops; Phase noise; Power line communications; Power system modeling; Programmable control; Signal to noise ratio; Working environment noise; digital phased-locked loop; impulsive noise; max a posteriori; power line communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-3883-9

Electronic_ISBN

978-1-4244-3884-6

Type

conf

DOI

10.1109/ICASID.2009.5276936

Filename

5276936