A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications

A major source of close-in phase noise in DeltaSigma fractional-N frequency synthesizers is noise-folding due to the nonlinear behavior of the combined phase- frequency detector (PFD)/charge-pump (CP) circuit. A fractional-N PLL with an analog discrete-time PFD and loop filter, along with an error canceling DAC is utilized to alleviate the impact of DeltaSigma quantization error and nonlinearities on the phase noise and spurious emissions. A two-state type-I loop replaces the more conventional type-ll charge-pump PLLs. The type-I loop shifts the operating point of the phase detector away from the nonlinear region (i.e., close to zero phase error), thus eliminating the need for special CP linearization techniques. In PLL architecture, a third-order re-quantization path along with an 8b current-steering DAC reduces quantization noise induced phase error by more than 20 dB, enabling a wide loop bandwidth of 1 MHz. The two-state PFD drives a PMOS current source, integrating phase error across the sampling capacitor. PLL can enable data-weighted averaging in order to achieve DEM (dynamic-element matching) between the PFD path and the noise-cancellation path. The synthesizer is fabricated in a 1P6M 0.18 mum CMOS process and draws 26 mA from a 1.8V supply. A VCO with a PMOS tail biased topology is chosen for this design.