Title :
Realistic linked memory cell array faults
Author :
Van De Goer, A.J. ; Gaydadjiev, G.N.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
The problem of designing memory tests is to establish a relevant set of fault models only consisting of those faults which are shown to be possible to occur in practice. Thereafter, it is a challenge to the test designer to design an optimum test covering the faults of the established fault models. A new fault model, the disturb fault model, is introduced. The notation of linked faults is established and it is shown that march tests can only detect a subset of all linked faults. Thereafter, the universe of linked faults is reduced to the set of realistic linked faults. Last, the effectiveness of the realistic linked fault model is shown via new tests with a higher fault coverage and a shorter test length
Keywords :
SRAM chips; automatic testing; cellular arrays; circuit analysis computing; fault diagnosis; integrated circuit modelling; SRAM; disturb fault model; fault models; functional faults; higher fault coverage; linked faults; march tests; memory tests design; optimum test; realistic linked memory cell array faults; shorter test length; single cell faults; Computer architecture; Costs; Electronic mail; Fault detection; Joining processes; Marine vehicles; Production; Semiconductor device testing; Semiconductor memory; Shipbuilding industry;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555157
