A testable NORA CMOS serial-parallel multiplier

The authors present a NORA CMOS serial-parallel multiplier which is testable and has the capability of self-checking. The error detection of the multiplier is done at two levels: (1) checking the entire multiplication process as a whole at the system level and (2) testing each individual cell module. Residue codes are used to detect error at the system level. A NORA CMOS testing technique is used for the error detection at the cell (or circuit) level. Both the system-level and the circuit-level error detection circuit for multipliers of different sizes are evaluated in terms of area and time. A prototype of a testable multiplier with 8-bit multiplicand and 8-bit multiplier implemented with 4 μm-CMOS technology is also presented. The circuit-level error detection occupies only 11.5% of the total area. The additional time for error detection occupies only 11.1% of the total computational time