Delta-sigma A/D convertor with reduced sensitivity to op amp noise and gain

Switched-capacitor techniques are presented which compensate for noise and finite-gain limitation in second-order DSMs (delta-sigma modulators). Hand analysis and computer simulations show great promise for these new techniques, and preliminary tests conclusively show that the gain compensation is extremely promising, especially for low-power supply voltages. Test ICs containing the DSMs were fabricated in a 3-μm digital CMOS process. Class AB op amps were used in the DSMs; a low-gain, higher-speed version was used in the gain-compensated circuit. Results from preliminary tests show that the delta-sigma modulators presented are functional, but design and modeling errors combined with widely varying process parameters severely limited the op amp performance, causing the op amp settling time to be much longer than expected