Real-time equalization of A/D converter nonlinearities

A report is presented on a design, implemented with current technology, of a real-time compensator circuit. The author demonstrates the feasibility of using the phase-plane approach for real-time equalization of analog nonlinearities in the digital domain. It is shown that such compensation schemes have the potential to improve performance by removing slew-rate-dependent errors in the critical sample-hold circuits in sampling A/D converters. Linearity, as measured by the SFDR (spurious-free dynamic range), improved by more than 2 b over most of the Nyquist bandwidth for a 12-b, 5-MSps state-of-the-art A/D converter