DocumentCode :
1618862
Title :
A low noise, fast set-up low-dropout regulator in 65nm technology
Author :
Yongqiang Xiao ; Wengao Lu ; Meng Chen ; Yacong Zhang ; Zhongjian Chen
Author_Institution :
Dept. of Microelectron., Peking Univ., Beijing, China
fYear :
2012
Firstpage :
1
Lastpage :
3
Abstract :
Low noise, fast set-up low-dropout (LDO) regulators are critical for noise-sensitive analog blocks, such as ADCs, PLLs, and RF SoC, etc. This paper presents a two-stage LDO regulator with low output noise, fast set-up, and high power supply rejection ratio (PSRR), based on internal noise filter with a novel fast set-up module, which solves dc shift problems. The proposed LDO is fabricated in a standard 65nm CMOS process. Measurement showed that output noise rms voltage is about 50nV/rtHz ranging from 10Hz to 100 KHz, set-up time is less than 20us, and PSRR is 65B at 1 KHz and 54dB at 1MHz.
Keywords :
CMOS integrated circuits; power electronics; voltage regulators; CMOS process; PSRR; fast set-up low-dropout regulator; high power supply rejection ratio; low noise low-dropout regulator; noise-sensitive analog blocks; size 65 nm; Capacitors; Noise; Regulators; Resistors; System-on-chip; Transistors; Voltage control; PSRR; fast set-up; internal filter; low-dropout regulator; output noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
Type :
conf
DOI :
10.1109/EDSSC.2012.6482827
Filename :
6482827
Link To Document :
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